學習心得

終於還是有把第一階段"行為模式設計"給做出來。

這堂課還算是學了不少東西，獲益良多啦！除了上課聽老師講 Verilog 程式和設計結構的正課外，尤其喜歡在課堂上，聽老師說些有關職場這方面事情，和一些有關於目前IC設計界的訊息。老師說過，設計這種東西，如果一個不小心弄不好，一旦量產後，等於是砸了幾千萬元而做出一堆石頭，這句話我聽了真的超貼切，也很現實！畢竟職場上本來就一直遵循『物競天擇、適者生存』的規則在遊戲著。要想賺大錢，就應該付出更多心力與工夫才是！

連上3學期陳老師的課，要畢業了，最後，還是要感謝陳老師一直以來辛苦的付出及教悔~！！

乘法機___程式模擬圖

Test： 9*8=48(十六進位)

乘法機___ASM圖

乘法機___程式內容

`define NUM_STATE_BITS 2
`define IDLE 2'b00
`define INIT 2'b01
`define COMPUTE1 2'b10
`define COMPUTE2 2'b11

module cl(clk);
parameter TIME_LIMIT = 110000; //1250;
output clk;
reg clk;

initial
clk = 0;

always
#50 clk = ~clk;

always @(posedge clk)
if ($time > TIME_LIMIT) #70 $stop;

endmodule

module slow_div_system(pb,ready,x,y,r2,sysclk);
input pb,x,y,sysclk;
output ready,r2;
wire pb;
wire [11:0] x,y;
reg ready;
reg [11:0] r1,r2;
reg [`NUM_STATE_BITS-1:0] present_state;

always
begin
@(posedge sysclk) enter_new_state(`IDLE);
r1 <= @(posedge sysclk) x;
ready = 1;
if (pb)
begin
@(posedge sysclk) enter_new_state(`INIT);
r2 <= @(posedge sysclk) 0;
while (r2 != y*r1)
begin
@(posedge sysclk) enter_new_state(`COMPUTE2);
r2 <= @(posedge sysclk) r2 + r1;
@(posedge sysclk) enter_new_state(`COMPUTE1);
r1 <= @(posedge sysclk) r1;
end
end
end
task enter_new_state;
input [`NUM_STATE_BITS-1:0] this_state;
begin
present_state = this_state;
#1 ready=0;
end
endtask

always @(posedge sysclk) #20
$display("%d r1=%d r2=%d pb=%b ready=%b", $time, r1,r2, pb, ready);
endmodule

module top;
reg pb;
reg [11:0] x,y;
wire [11:0] quotient;
wire ready;
integer s;
wire sysclk;

cl #20000 clock(sysclk);
slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);

initial
begin
pb= 0;
x = 0;
y = 3;
#250;
@(posedge sysclk);
for (x=0; x<=4; x = x+1)
begin
@(posedge sysclk);
pb = 1;
@(posedge sysclk);
pb = 0;
@(posedge sysclk);
wait(ready);
@(posedge sysclk);
if (x*y === quotient)
$display("ok");
else
$display("error x=%d y=%d x*y=%d quotient=%d",x,y,x*y,quotient);
end
$stop;
end
endmodule

除法機___ASM 圖 & 程式模擬圖 & 程式內容

`define NUM_STATE_BITS 2
`define IDLE 2'b00
`define INIT 2'b01
`define COMPUTE1 2'b10
`define COMPUTE2 2'b11

module cl(clk);
parameter TIME_LIMIT = 110000; //1250;
output clk;
reg clk;

initial
clk = 0;

always
#50 clk = ~clk;

always @(posedge clk)
if ($time > TIME_LIMIT) #70 $stop;

endmodule

module slow_div_system(pb,ready,x,y,r2,sysclk);
input pb,x,y,sysclk;
output ready,r2;
wire pb;
wire [11:0] x,y;
reg ready;
reg [11:0] r1,r2;
reg [`NUM_STATE_BITS-1:0] present_state;

always
begin
@(posedge sysclk) enter_new_state(`IDLE);
r1 <= @(posedge sysclk) x;
ready = 1;
if (pb)
begin
@(posedge sysclk) enter_new_state(`INIT);
r2 <= @(posedge sysclk) 0;
while (r1 >= y)
begin
@(posedge sysclk) enter_new_state(`COMPUTE1);
r1 <= @(posedge sysclk) r1 - y;
@(posedge sysclk) enter_new_state(`COMPUTE2);
r2 <= @(posedge sysclk) r2 + 1;
end
end
end
task enter_new_state;
input [`NUM_STATE_BITS-1:0] this_state;
begin
present_state = this_state;
#1 ready=0;
end
endtask

always @(posedge sysclk) #20
$display("%d r1=%d r2=%d pb=%b ready=%b", $time, r1,r2, pb, ready);
endmodule

module top;
reg pb;
reg [11:0] x,y;
wire [11:0] quotient;
wire ready;
integer s;
wire sysclk;

cl #20000 clock(sysclk);
slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);

initial
begin
pb= 0;
x = 0;
y = 7;
#250;
@(posedge sysclk);
for (x=0; x<=14; x = x+1)
begin
@(posedge sysclk);
pb = 1;
@(posedge sysclk);
pb = 0;
@(posedge sysclk);
wait(ready);
@(posedge sysclk);
if (x/y === quotient)
$display("ok");
else
$display("error x=%d y=%d x/y=%d quotient=%d",x,y,x/y,quotient);
end
$stop;
end
endmodule

修改除法機 → 失敗

Test：5*3 → 失敗 < 我要再接再厲 >"< >

第一天上課

這學期又再度修陳老師的課囉！
今天第一天來上課，就聽說老師指定用書的中文版............絕版了~!! 泣 >"<
一直考慮到底要不要買原文版...........沉思中~~~~~~~~~~~~~~!!